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MPEG-4 Encoder
The MPEG-encoder core provides an efficient hardware implementation of ISO/IEC
14496-2 standard video compression. It supports a wide range of image sizes ,
making it suitable for applications from video conferencing to real-time VGA
video streaming. Advanced functions like DCT are built-in, and it requires only
an external SDRAM for frame storage and any processor for supervision. Main
Feature list:
Fully compatible with the ISO/IEC 14496-2 specification
YCbCr 4:2:0 raster video input
I and P Video Object Planes output
Supports Advanced Simple Profile Level 1 to 5
Capable of processing full resolution video (beyond 4CIF)
Very low operational frequency: from ~3 MHz for QCIF @ 15 fps
Min Clock speed = 8 x the raw pixel clock Speed
DC prediction: Variable Bit Rate/Motion vector up to -16.0/+15.5 pixels (IVOP
and P-VOP support)/The processor includes IEEE-1180 compliant DCT/IDCT and type
1 quantizer/dequantizer
Glueless interface to SDRAM for frame storage
Digital Video Encoder
The Digital Video Encoder compliant multi-standard digital video encoder core
(M-DVE)
delivers a broadcast quality video for high performance multimedia/video
applications. It
is can take YCrCb, YUV. etc digital pixel data in CCIR 656 compliant order,
perform encoding, then propagate generated signal to composite (CVBS) and/or
S-video DAC interfaces.
Main Feature list:
Input digital pixel data compliant to CCIR601/CCIR656, accept YUV /YCrCb data in
4:2:2 mode;
PAL B/G and NTSC-M output formats;720x576 in PAL/ 720x480 in NTSC output
resolution;
Chrominance digital 5 pole LPFs; Luminance digital 3 pole LPF;
Chrominance 4x linear interpolator; Luminance 2x linear interpolator;
Sub-carrier phase integral error compensation;
SINC correction for the chrominance datapath;
Direct Digital Synthesizer with reduced cosine table;
16 bit internal signal processing;
Any DAC from 6 to 16 bits can be connected to CVBS and S-video digital
interfaces;
Voice Codec
Voice codec core! Main feature:
Complete digital 'back-end' for Sigma-Delta based G.711/G.712 voice codec-filter
Digital signal processing minimizes analogue front end requirements
8-bit parallel PCM interface: u-law and A-law configurable
Targeted at gate array, standard-cell
VGA
The VGA Controller Core provides VGA capabilities for embedded systems. It
supports CRT/LCD displays with programmable resolutions and video timings..
Main feature list:
Support almost all CRT and LCD displays
32bpp, 24bpp and 16bpp color modes support
programmable video timing/resolutions and control signals polarization levels
Separate VSYNC/HSYNC and combined CSYNC synchronization signals
8bpp grayscale and 8bpp pseudo-color modes
Supports video- and/or color-lookup-table bank switching during vertical retrace
Per cursor user selectable resolutions, 23x23 pixels and 64x64 pixels
Support for 3D cursors, support up to two hardware cursors
Triple display support
widely range of input clock frequencies
V4.2
V.42 bits compression engine! Main feature:
Compliant with CCITT Recommendation V.42 bis
Transfer statistics generated
Configurable RAM interface
Reduces processor time for compression by 95%
Programmable dictionary size and compression parameters
Targeted at gate array, standard-cell
Reed-Solomon
A core to implement ECC algorithm, main feature list:
4-bit ECC
Encoding and decoding included
CSC
The CSC core is a compact, high-performance, highly flexible color space
conversion core, often used for transferring data between devices that use
different color space models. For example, to transfer a TV image to a computer
monitor, you may need to convert the image from the Y'CrCb color space to the
R'G'B' color space.
Main feature list:
Supports a variety of conversion functions:
Computer R'G'B' to Y'CrCb
Y'CrCb to computer R'G'B'
Computer R'G'B' to Y'UV
Y'UV to computer R'G'B'
Studio video R'G'B' to Y'CrCb
Y'CrCb to studio video R'G'B'
Y'IQ to Y'UV
conversion parameters configurable
Supports signed and unsigned input data widths up to 32 bits
Output precision configurable
rounding, saturation, and truncation
DES/3-DES
The DES/3-DES core is a fully compliant implementation of the DES encryption
algorithm, supports both encryption and decryption, support ECB, CBC and Triple
DES versions.
Main feature list:
Support encryption and decryption. Support DES/3-DES .
Fully compliant 56-bit DES implementation. Support 112/ 168-bit triple des keys.
For DES, Encryption/decryption performed in 16 cycles; for 3-DES, Encryption and
decryption 48 clock cycles.
Suitable for Electronic Codebook (ECB), Cipher Block Chaining (CBC), CFB and OFB
implementations No dead cycles for key loading or mode switching.
Sustained bit rate is 4 x clock speed.
No dead cycles for key loading or mode switching.
Suitable for data security applications.
Fully synchronous design.
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